A 2.7pJ/cycle 16MHz SoC with 4.3nW Power-Off ARM Cortex-M0+ Core in 28nm FD-SOI

Guénolé Lallement (1, 2) , Fady Abouzeid (1) , Martin Cochet (2, 1) , Jean-Marc Daveau (1) , Philippe Roche (1) , Jean-Luc Autran (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence

—This work presents a System-on-Chip designed for Energy-Harvested applications. It embeds an ARM Cortex-M0+ microcontroller, 4 KB RAM, 4 KB ROM, an ultra-low power frequency synthesizer, a custom power switch, and a Power Management Unit enabling Active and Sleep modes. The system fabricated in 28 nm FD-SOI technology achieves 2.7 pJ/cycle at 16 MHz during active mode, and the core consumes 4.3 nW during deep sleep mode. The system operates at a fixed voltage of 0.5 V, and can switch from Active and Sleep/Deep Sleep modes, adjusting the frequency from 16 MHz to 8 MHz or 32 kHz in one cycle upon energy availability. By combining frequency/power switching with extra Reverse Body-Biasing the system power consumption is reduced by 53% and 98% in respectively sleep and deep sleep modes.

Domaines: Micro et nanotechnologies/Microélectronique

Guénolé Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, et al.. A 2.7pJ/cycle 16MHz SoC with 4.3nW Power-Off ARM Cortex-M0+ Core in 28nm FD-SOI. ESSCIRC 2017, Sep 2017, Leuven, Belgium. ⟨hal-01788172⟩