A 0.40 pJ/cycle 981 μm2 Voltage Scalable Digital Frequency Generator for SoC Clocking

Martin Cochet (1, 2) , Sylvain Clerc (2) , Fady Abouzeid (3) , Guénolé Lallement (2, 1) , Philippe Roche (2) , Jean-Luc Autran (1)

1 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2 ST-CROLLES - STMicroelectronics [Crolles]
3 STMicroelectronics

This work presents a compact voltage and frequency scalable clock generator for low-power digital SoC clock-ing. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1 V with measured jitter from 2.0% to 5.1% UI. Its low power consumption of 0.40 pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency changes makes this circuit an alternative to PLLs for fast Dynamic Voltage and Frequency Scaling (DVFS) strategies in low power SoCs.

Domains: Engineering Sciences [physics]; Micro and nanotechnologies/Microelectronics

Martin Cochet, Sylvain Clerc, Fady Abouzeid, Guénolé Lallement, Philippe Roche, et al.. A 0.40 pJ/cycle 981 μm2 Voltage Scalable Digital Frequency Generator for SoC Clocking. 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC 2017), Nov 2017, Seoul, South Korea. ⟨hal-01788358⟩