A 0.40 pJ/cycle 981 μm2 Voltage Scalable Digital Frequency Generator for SoC Clocking

Abstract : This work presents a compact voltage and frequency scalable clock generator for low-power digital SoC clock-ing. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1 V with measured jitter from 2.0% to 5.1% UI. Its low power consumption of 0.40 pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency changes makes this circuit an alternative to PLLs for fast Dynamic Voltage and Frequency Scaling (DVFS) strategies in low power SoCs.