Conference papers
A 0.40 pJ/cycle 981 μm2 Voltage Scalable Digital Frequency Generator for SoC Clocking
Abstract : This work presents a compact voltage and frequency scalable clock generator for low-power digital SoC clock-ing. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1 V with measured jitter from 2.0% to 5.1% UI. Its low power consumption of 0.40 pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency changes makes this circuit an alternative to PLLs for fast Dynamic Voltage and Frequency Scaling (DVFS) strategies in low power SoCs.
Cited literature [9 references]
https://hal-amu.archives-ouvertes.fr/hal-01788358
Contributor : Jean-Luc Autran <>
Submitted on : Wednesday, May 9, 2018 - 8:27:18 AM
Last modification on : Thursday, May 10, 2018 - 2:13:30 AM
Long-term archiving on: : Monday, September 24, 2018 - 12:00:40 PM
Contributor : Jean-Luc Autran <>
Submitted on : Wednesday, May 9, 2018 - 8:27:18 AM
Last modification on : Thursday, May 10, 2018 - 2:13:30 AM
Long-term archiving on: : Monday, September 24, 2018 - 12:00:40 PM
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A-SSCC2017.pdf
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