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A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed Train

Chen Liu 1 Xizheng Guo Rui Ma 2 Zhongliang Li 3, 4 Franck Gechter 5 Fei Gao 6
1 College of Mechanical and Electronic Engineering [Yangling]
2 HKUST - Hong Kong University of Science and Technology
3 LIS - Laboratoire d'Informatique et Systèmes
4 PECASE - Pronostic/Diagnostic Et CommAnde : Santé et Energie
LIS - Laboratoire d'Informatique et Systèmes
5 FEMTO-ST - Franche-Comté Électronique Mécanique, Thermique et Optique - Sciences et Technologies (UMR 6174)
6 NHCS - National Heart Centre Singapore
Abstract : Hardware-in-the-loop (HIL) test provides a time saving and safe environment for testing high-power electronic systems. But the main difficulty for the HIL test of power electronic system lies on the modeling of the complex and highpower system. This paper proposes a modeling method of the electrical system of high-speed train. With this method, the HIL test platform using field-programmable gate array boards is built. Besides, in order to meet the computing power requirement of the system modeling, we simulate the whole system using two dSPACE simulators and inside each dSPACE simulator, a multiprocessor system is achieved through Gigalink connection. The whole HIL system can be used to evaluate both the hardware and software performance of traction control unit and auxiliary control unit. The HIL results under steady state and transient conditions demonstrate modeling accuracy and provide a detailed insight into its development.
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https://hal-amu.archives-ouvertes.fr/hal-02004131
Contributor : Zhongliang Li <>
Submitted on : Friday, February 1, 2019 - 3:39:54 PM
Last modification on : Thursday, June 3, 2021 - 2:50:04 PM

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UNIV-AMU | CNRS | LIS-LAB | UNIV-TLN | TDS-MACS | UNIV-BM | UNIV-FCOMTE | UNIV-BM-THESE | FEMTO-ST

Citation

Chen Liu, Xizheng Guo, Rui Ma, Zhongliang Li, Franck Gechter, et al.. A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed Train. IEEE Transactions on Transportation Electrification, Institute of Electrical and Electronics Engineers, 2018, 4 (4), pp.912-921. ⟨10.1109/TTE.2018.2866696⟩. ⟨hal-02004131⟩

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