A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed Train

Chen Liu 1 Xizheng Guo Rui Ma 2 Zhongliang Li 3 Franck Gechter 4 Fei Gao 5
1 College of Mechanical and Electronic Engineering [Yangling]
2 HKUST - Hong Kong University of Science and Technology
3 LIS - Laboratoire d'Informatique et Systèmes
4 FEMTO-ST - Franche-Comté Électronique Mécanique, Thermique et Optique - Sciences et Technologies (UMR 6174)
5 NHCS - National Heart Centre Singapore
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Journal articles
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https://hal-amu.archives-ouvertes.fr/hal-02004131
Contributor : Zhongliang Li <>
Submitted on : Friday, February 1, 2019 - 3:39:54 PM
Last modification on : Wednesday, September 25, 2019 - 1:22:25 AM

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UNIV-AMU | CNRS | LIS-LAB | UNIV-TLN | TDS-MACS | UNIV-BM | UNIV-FCOMTE | UNIV-BM-THESE | FEMTO-ST

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Chen Liu, Xizheng Guo, Rui Ma, Zhongliang Li, Franck Gechter, et al.. A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed Train. IEEE Transactions on Transportation Electrification, Institute of Electrical and Electronics Engineers, 2018, 4 (4), pp.912-921. ⟨10.1109/TTE.2018.2866696⟩. ⟨hal-02004131⟩

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