Impact of Line Resistance Combined with Device Variability on Resistive RAM Memories - Archive ouverte HAL Access content directly
Journal Articles Advances in Science, Technology and Engineering Systems Journal Year : 2018

Impact of Line Resistance Combined with Device Variability on Resistive RAM Memories

Abstract

In this paper, the performance and reliability of oxide-based Resistive RAM (ReRAM) memory is investigated in a 28nm FDSOI technology versus interconnects resistivity combined with device variability. Indeed, common problems with ReRAM are related to high variability in operating conditions and low yield. At a cell level ReRAMs suffer from variability. At an array level, ReRAMs suffer from different voltage drops seen across the cells due to line resistances. Although research has taken steps to resolve these issues, variability combined with resistive paths remain an important characteristic for ReRAMs. In this context, a deeper understanding of the impact of these characteristics on ReRAM performances is needed to propose variability tolerant designs to ensure the robustness of the technology. The presented study addresses the memory cell, the memory word up to the memory matrix.
Fichier principal
Vignette du fichier
ASTESJ_030102.pdf (1.23 Mo) Télécharger le fichier
Origin : Publication funded by an institution
Loading...

Dates and versions

hal-02335339 , version 1 (28-10-2019)

Licence

Attribution - ShareAlike - CC BY 4.0

Identifiers

Cite

Hassen Aziza, Pierre Canet, Jérémy Postel-Pellerin. Impact of Line Resistance Combined with Device Variability on Resistive RAM Memories. Advances in Science, Technology and Engineering Systems Journal, 2018, 3 (1), pp.11-17. ⟨10.25046/aj030102⟩. ⟨hal-02335339⟩
99 View
69 Download

Altmetric

Share

Gmail Facebook Twitter LinkedIn More