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Impact of Line Resistance Combined with Device Variability on Resistive RAM Memories

Abstract : In this paper, the performance and reliability of oxide-based Resistive RAM (ReRAM) memory is investigated in a 28nm FDSOI technology versus interconnects resistivity combined with device variability. Indeed, common problems with ReRAM are related to high variability in operating conditions and low yield. At a cell level ReRAMs suffer from variability. At an array level, ReRAMs suffer from different voltage drops seen across the cells due to line resistances. Although research has taken steps to resolve these issues, variability combined with resistive paths remain an important characteristic for ReRAMs. In this context, a deeper understanding of the impact of these characteristics on ReRAM performances is needed to propose variability tolerant designs to ensure the robustness of the technology. The presented study addresses the memory cell, the memory word up to the memory matrix.
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Hassen Aziza, Pierre Canet, Jérémy Postel-Pellerin. Impact of Line Resistance Combined with Device Variability on Resistive RAM Memories. Advances in Science, Technology and Engineering Systems Journal, Advances in Science Technology and Engineering Systems Journal (ASTESJ), 2018, 3 (1), pp.11-17. ⟨10.25046/aj030102⟩. ⟨hal-02335339⟩

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