Advanced TCAD Simulation of Tunnel Oxide Degradation for EEPROM Applications

F. Matteo (1) , R. Simola (1) , J. Postel-Pellerin (2) , K. Coulie (2)

1 ST-ROUSSET - STMicroelectronics [Rousset]
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence

In this paper we have simulated dynamic Constant Voltage Stress (CVS) and subsequent degradation of MOS capacitor representative of Non-Volatile Memory (NVM) devices. Oxide degradation was modelled through trap defects generation at SiO 2 /Si interface and SiO 2 bulk. A very good agreement was obtained between simulation and experimental data.

Domaines: Micro et nanotechnologies/Microélectronique

F. Matteo, R. Simola, J. Postel-Pellerin, K. Coulie. Advanced TCAD Simulation of Tunnel Oxide Degradation for EEPROM Applications. IEEE 4th International Conference on Dielectrics (ICD 2022), Jul 2022, Palerme, Italy. pp.764-768, ⟨10.1109/ICD53806.2022.9863611⟩. ⟨hal-03941192⟩