A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's

Dominique Vuillaume (1) , Marchetaux J.-C. , Lippens P.-E. , Bravaix A. (2) , Boudou A.

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
2 ISEN Toulon

The creation of defects by hot-carrier effect in submicrometer (0.85µm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptor-like oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from Vd/8 to Vd/) by hot-hole and/or hot-electron injections, and their generation rates (1E-9 and 1E-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the Id-Vg degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the Id-Vg degradation.

Domains: Engineering Sciences [physics]

Dominique Vuillaume, Marchetaux J.-C., Lippens P.-E., Bravaix A., Boudou A.. A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's. IEEE Transactions on Electron Devices, 1993, 40 (4), ⟨10.1109/16.202790⟩. ⟨hal-03022897⟩