A 28nm FD-SOI Standard Cell 0.6-1.2V Open-Loop Frequency Multiplier for Low Power SoC Clocking

Martin Cochet (1, 2) , Sylvain Clerc (2) , Mehdi Naceur , Pierre Schamberger , Damien Croain , Jean-Luc Autran (1) , Philipe Roche (2)

1 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2 ST-CROLLES - STMicroelectronics [Crolles]

This paper presents a new design for SoC clocking based on open-loop frequency multiplication. The architecture, fully implemented in 28nm FD-SOI standard cells, achieves frequency tracking within one input reference period making it a promising candidate for Dynamic Voltage and Frequency Scaling (DVFS) schemes. A calibration scheme is implemented for wide voltage range (0.6-1.2V) operation and to offset P&R and variability induced mismatch. Measurements at 0.6V (0.8/0.4V FBB) show a Fmax of 93MHz with a power of 2.91mW/MHz and a jitter of 2.7 % UI.

Domaines: Micro et nanotechnologies/Microélectronique

Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, et al.. A 28nm FD-SOI Standard Cell 0.6-1.2V Open-Loop Frequency Multiplier for Low Power SoC Clocking. 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, Unknown, Unknown Region. pp.1206-1209. ⟨hal-01434957⟩